As Moore law proceeds to the technical node of 22 nm, the traditional planar field effect transistor can not meet the requirements of low power consumption and high performance. In order to overcome the short channel effect and improve the drive current density, field effect transistors with a fin-shaped channel (FinFET) of 3-dimensional structure has been introduced into the large scale integrated circuits. This structure has very excellent immunity to short channel effect and very high drive current owing to the large gate-controlling area and narrow channel depletion region.
There are many challenges in FinFET fabrication to limit the applications of FinFET in large scale integrated circuits. One of the difficulties lies in the etching of the 3-dimesional gate profile, which is due to the surface fluctuation occurred when depositing gate materials. The gate materials have large surface fluctuation since they are deposited on 3-dimensional fin-shaped silicon strips. Thus, it is difficult to focus during the lithography process and it is difficult to completely remove the gate materials on sidewalls of the fin unless using a large over-etching process. However, the large over-etching process may cause damage to the silicon active region. This problem is serious especially when employing a high resolution lithography process below 22 nm. Hence, the product yield is restricted.
Several methods have been proposed to perform a planarization process firstly, and then to perform a photolithgraphy process and an etching process. For example, it is disclosed in U.S. patent publication US2005056845-A1 that an entire planar gate material is obtained by covering the fin with two gate layers of different materials, and then performing a planarization process to the first gate layer through a chemical mechanical polishing method. This method requires firstly covering the top of the fin with a layer of insulation dielectric to protect the top of the fin from damage. However, this method can neither form triple gate structure nor reduce the burden of the gate etching process.
The problem caused by the gate etching residue on sidewalls is solved in U.S. patent publication US2005170593-A1 by Damascus fake-gate process, that is, by etching the trench with a gate electrode mask and then refilling the gate material, which may address the problem caused by the gate etching residue on fin sidewalls. Thus, the reliability of product is improved. However, this method can not form the triple gate structure, and the gate strip width on the top of the fin and the gate strip width on sidewalls can not be formed in a self-aligned manner.